The present inventive concepts relate to testing resistive type memory circuits, and more particularly to stress testing, retention testing, functional testing, and fast test initialization, and for improving the reliability of memory circuits.
Resistive type memories encompass a new generation of non-volatile memory and are expected to become dominant event to the point of eventually replacing conventional non-volatile memories such as flash memory, Erasable Programmable Read Only Memory (EPROM), and the like. It is expected that resistive type memories might also eventually replace traditional volatile memories such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and other similar volatile memory technologies.
The conventional non-volatile memory technologies can suffer from performance and long term reliability issues while the conventional volatile memory technologies suffer from the inability to permanently store data. On the other hand, resistive type memories have many of the most desirable features of flash and DRAM, without many of the drawbacks. Resistive type memories can include, for example, spin transfer torque (STT) magnetoresistive random-access memory (MRAM), MRAM (of the non-STT variety), phase change RAM, memristor RAM, ReRAM, CBRAM, and the like. By combining the permanent storage benefits of non-volatile memory with the high performance and reliability characteristics of DRAM or other volatile type memories, resistive type memories are positioned for an important role in the marketplace.
Prior to entering the field, memory circuits must be tested. Otherwise, memory cell infant mortality rates would be unacceptably high. Such failures can be disruptive to computer equipment, embedded devices, software algorithms, and so forth. As the size and density of memory circuits increases, the importance for effective, thorough and efficient testing proportionally increases.
Resistive type memory cells in their simplest form include a variable resistor and a transistor. Using a standard convention, a low resistance state is defined as being a logic ‘0’, or low logic state, and a high resistance state is defined as being a logic ‘1’, or high logic state. It will be understood that other conventions can be used, for example, where a low resistance state is defined as logic ‘1’ and a high resistance state is defined as logic ‘0’.
Resistive type memory cells are designed to have a critical switching voltage or current. For example, when sufficient current is passed through the cell to satisfy the switching current level, then the cell will typically switch from one logic value to another. Switching cells from a high logic state to a low logic state, or from a low logic state to a high logic state, is probabilistic. In other words, there is a given probability that the switching voltage or current will change a memory cell from a ‘1’ to a ‘0’ or vice versa. In some cases, errors can occur when attempting to read or write a memory cell. For example, when reading a memory cell, sometimes the cell accidentally switches when it is not expected to switch. Read disturb of a memory cell occurs when the memory cell data changes unintentionally during a read operation. Read disturb tends to happen when the read error rate of a memory cell is unusually high. When writing a memory cell, sometimes the cell doesn't switch when it is expected to switch. Write errors occur when the write error rate of a memory cell is unusually high.
Some memory cells may exhibit a higher error rate than others. If the aggregate error rate of a memory device is too high, then the memory devices cannot go into production. Conventional testing methods, which may be effective for DRAM, flash, and other traditional memories, generally do not translate to resistive type memories, nor are they conducive to the unique physical characteristics of resistive memories such as STT-MRAM. Moreover, as the size and density of resistive type memories continues to increase, the difficulty and time expended for efficiently testing the resistive type memories also increases. It would be desirable to apply massive parallel screening to reduce test time and cost. It would also be desirable to provide techniques for retention testing, functional testing, fast initialization, and for improving the reliability of memory circuits.